1. Field of the Invention
The present invention relates to a semiconductor memory device and a driving method of a semiconductor memory device.
2. Related Art
In recent years, an FBC (Floating Body Cell) memory device is available as a semiconductor memory device which is expected to replace a DRAM. The FBC memory device includes an N-type MOS transistor having a floating body on an SOI (Silicon On Insulator) substrate, as a memory cell, and stores data “1” or “0” depending on a number of holes accumulated in this body area. When the memory cell is an N-type FET, for example, a state that the number of holes accumulated in the body area is large is expressed by data “1”, and a state that the number of holes accumulated in the body area is small is expressed by data “0”. As a result, a threshold voltage of a memory cell that stores data “1” becomes low. A threshold voltage of a memory cell that stores data “0” becomes high.
When a memory cell is set to an on state, a part of electrons within an inversion layer is trapped at an interface potential at the interface between a gate oxide film and the body area. Positive holes accumulated in the body area are combined with electrons, and disappear. When this is repeated, the state of data “1” in non-selected memory cells change to data “0”. This is called a charge pumping phenomenon.
Therefore, the FBC memory device requires a periodical refresh operation of the cells of data “1”.
However, in the case of the FBC, a threshold value of the memory cell storing data “1” is low, and a threshold value of the memory cell storing data “0” is high. Therefore, a CMOS cross-coupled latch sense amplifier provided between a pair of sense nodes needs to theoretically inverse data and write back (restore) the data into a memory cell, after latching a potential difference of sense nodes in the data reading. For example, during the reading, data of a pair of bits BL and BBL are transmitted to a pair of sense nodes SN and BSN, respectively, and data of a pair of sense nodes SN and BSN are transmitted to a pair of bit lines BBL and BL during the writing. In order to restore data by inversing the data at the refresh time, transfer gates TG2 are provided to connect between the bit line BL and the sense node BSN and between the bit line BBL and the sense node SN, in addition to transfer gates TG1 that connect between the bit line BL and the sense node SN and between the bit line BBL and the sense node BSN. During the reading, the gate TG1 is on and the gate TG2 is off. During the restoring, the gate TG2 is on and the gate TG1 is off.
In this case, in a case of shifting from a reading operation to a restore operation, the timing of turning off the gate TG1 and the timing of turning off the latch sense amplifier become a problem. Conventionally, there are a specification 1 for simultaneously turning off the gate TG1 and the latch sense amplifier or turning off the gate TG1 earlier, and a specification 2 for turning off the latch sense amplifier earlier than the gate TG1.
According to the specification 1, the sense node is disconnected from the bit line at the time of latching data. Therefore, capacity of the sense node becomes small, and data on the sense node becomes unstable. As a result, there is a risk that the latch sense amplifier recognizes data by error. On the other hand, according to the specification 2, when the latch sense amplifier latches data, the sense node is connected to the bit line. Therefore, there is a risk that an inverse logic signal is transmitted to the bit line. Accordingly, the inverse logic data is stored into the memory cell at the data latch time. When data “1” is written back at the refresh time, a drain voltage is weaker than that when data “1” is written. Therefore, when data “0” is once written back by error, there is a high potential that the data “0” cannot be returned to data “1”.